A testing strategy known as “partial good” is increasingly used by integrated circuit (chip) manufacturers in an attempt to increase yields of complex integrated circuits. Partial good methodologies include testing individual sections of chip circuitry, marking them as functional or non-functional (failed), and isolating the non-functional sections to prevent them from interfering with the operation of the functional sections.
Scan latch chains are often used to facilitate access to latches within individual sections of circuitry (cores), and are used to initialize, test, and debug both individual cores as well as the entire chip. Each core typically has a scan chain that includes latches useful for performing functions within the core.
In a partial good strategy, failing circuit elements within a core may require that the core, including its scan latches, be disabled, and that core's section of the scan chain be bypassed. The subsequent bypassing (shortening) of the overall chip scan chain may cause operational difficulties for both the hardware and software external to the chip which manages the chip scan activity.